Modern personal computers generally comprise a graphics controller that controls the display of data, and which uses a frame buffer memory. This frame buffer is typically a 1 MB memory linked to the graphics controller through a 32 bit bus. When a 2 MB memory is used, a 64 bit bus is used. Computers also comprise system memory used by the processor for running the operating system and applications. This memory is usually accessed through a 64 bit bus.
UMA or Unified Memory Architecture is an architecture where the frame buffer memory space used by the graphics controller is actually part of the system memory. The advantages of such an architecture are the following. First, UMA permits reduction of the overall amount of memory necessary for a computer. Instead of having 16 MB of system memory and 1 MB of frame buffer, a computer only needs 16 MB shared between the system memory and the frame buffer. Second, UMA allows the graphics controller to use a 64 bit bus, even with only 1 MB of frame buffer.
The drawbacks of UMA are the poor performance, due to memory sharing and memory access collision between the graphics controller and the processor, and the fact that less system memory is available for the operating system.
Taking advantage of the improvement of silicon technology, it has been proposed to integrate the graphics controller into a single-chip chipset. The graphics controller thus has direct access to the processor bus. This provides a wider bus for the graphics controller, even with only 1 MB of frame buffer. FIG. 1 is a schematic view of an embodiment of such a UMA single-chip chipset of the prior art, with its related components. In FIG. 1, the single-chip chipset 1 comprises a peripheral bus controller 3, a memory controller 4, and a graphics controller 5. The chipset 1 is connected to a processor 6 through a processor bus 7, e. g. a 64 bit bus running at 66 MHz. It is also connected to a peripheral bus 8 through the peripheral bus controller 3. The peripheral bus is typically a bus of the PCI type. The chipset 1 is finally connected to the system memory 9, through a system bus 10, e.g. a 64 bit bus at 66 MHz.
As shown by arrows in FIG. 1, the graphics controller 5 has access to the system memory 9, through the memory controller 3 and the system bus 10. Part of the system memory, as explained above, is used as frame buffer. Such a UMA single-chip chipset is sold by . . . under the reference . . .
Such integration of the memory controller on the chipset gives a clear performance advantage, since the graphics controller sits directly on the processor bus. In the case of a 64 bit bus running at 66 to 100 MHz, this provides access to the graphics controller with a bandwidth of 528 to 800 MB; as a comparison a prior art graphics controller bus like the one provided under the tradename AGP allows a bandwidth of 533 MB. However, the chipset/graphics controller of FIG. 1 still presents the drawbacks of UMA, as described above.
There also exists a need today for increasingly higher resolution and colour depth, which requires more frame buffer memory, with a high impact on performance. The UMA architecture of FIG. 1 may provide such features if the size of the system memory is increased, but still presents the same drawbacks.
The object of the invention is to provide an architecture for personal computers, that overcomes the above described drawbacks of UMA, while providing high resolution, colour depth and performance.
Another object of the invention is to provide an easily upgradable architecture, that may easily be adapted to different types of configurations.